The present invention is generally directed to an apparatus and method for testing logic circuitry on an ink jet print head. More particularly, the invention is directed to testing an ink jet print head using a serial integrated scan-based test technique.
As with most integrated circuitry, the testability of ink jet heater chips is essential to gaining a better understanding of the design and process issues that lead to poor yield and high die costs. As the number if ink-ejecting nozzles per heater chip increases, logic circuits on the heater chip become more and more complex. As the amount and complexity of on-chip logic increases, so does the potential for faults. To identify and eliminate these faults, structured test methodologies are needed that provide controllability and observability of internal circuit nodes while not adding significant additional amounts of costly test logic circuitry to the chip. Generally, controllability is the ability to set and reset every internal node of an integrated circuit. Observability is the ability to observe, either directly or indirectly, the state of any internal circuit node.
What is needed is an ink jet print head heater chip which provides improved observability and controllability of its internal logic nodes, and testing techniques to take advantage of such observability and controllability.
The foregoing and other needs are met by an ink jet print head integrated circuit that receives print data related to an image to be printed, and receives test point data for testing internal logic nodes of the circuit. The circuit includes x number of switching devices, each having a serial input, a test point input, and a switch output. The switch output is coupled to the serial input when the switching device is in a first state, and coupled to the test point input when the switching device is in a second state. The circuit also includes n number of bit registers, each having a data input and a data output. The data input of x number of the bit registers is coupled to the switch output of a corresponding one of the x number of switching devices. The circuit includes a serial print data input for receiving a serial string of bits of the print data. The circuit further includes x number of test points coupled to the test point inputs of the x number of switching devices. The x number of test points are for receiving x number of parallel bits of the test point data. A test data output for outputting a serial string of bits of the x number of bits of the test point data is coupled to the data output of an nth of the n number of bit registers. Preferably, x is less than or equal to n.
Thus, the circuit comprises an n-bit shift register which operates in a print mode or a test mode. When the circuit is operating in the print mode, n bits of print data are serially scanned into the n bit registers and are then latched out to heater addressing logic circuitry in the print head to control a print operation. When the circuit is operating in the test mode, x bits of test point data from x test nodes in the print head are loaded in parallel into x number of the n bit registers and are then serially scanned out to the test data output. In this manner, a single shift register may be used to scan in print data and scan out test data, thereby providing observability and controllability of the internal logic nodes of the print head while minimizing the logic size and the number of input/output connections on the print head.
In another aspect, the invention provides an ink jet print head integrated circuit for receiving print data related to an image to be printed, and for receiving test point data for testing internal logic nodes of the circuit. The circuit includes a shift register having a serial print data input for receiving bits of the print data in a serial string, and a plurality of parallel print data outputs for outputting the bits of print data in parallel. The circuit also includes a plurality of parallel test point inputs for receiving bits of the test point data in parallel, and a serial test data output for outputting a serial string of the bits of the test point data. The circuit further includes a plurality of latch circuits, each having a latch input coupled to a corresponding one of the parallel print data outputs.
In yet another aspect, the invention provides a method for operating on print data related to an image to be printed by an ink jet print head, and for operating on test point data to determine whether faults exist in internal logic nodes of the ink jet print head. The method includes the following steps: (a) receiving bits of the test point data at test point inputs of a shift register in the print head; (b) shifting the bits of the test point data through the shift register; (c) outputting the bits of the test point data from a serial output of the shift register; (d) receiving a serial string of bits of the print data at a serial input of the shift register; (e) shifting the bits of the print data through the shift register; and (f) latching the bits of the print data from parallel outputs of the shift register.